Recently a digital signal processing has been generally applied to an image display. For example, when the analog signal of TV, etc. is subjected to an A/D conversion, there appears a false outline of a displayed image since the continuity of gradation is lost (quantization noise). Many liquid crystal TVs which employ LCDs as display elements also use A/D converters. Passive matrix panels for displaying moving pictures generally employ a method of subjecting a luminance signal to A/D conversion and thereafter converting the resulting digital signal into a pulse width, and it is known that active matrix panels employing MIM elements can also use a similar method (e.g., refer to Japanese Patent Publication No. 63 - 6855).
Many liquid crystal TVs employ a 4 - bit A/D converter for the purpose of miniaturization or securing portability. The number of gradations which can be displayed by 4 - bit data, however, is as few as 16, so that quantization noise is conspicuous.
FIG. 16 is a block diagram exemplifying a system for improving image quality using a dither method. In the system, a TV signal is input to the input terminal IN of a 4 - bit A/D converter 1, which supplies an A/D converted 4 - bit data to a memory 21 in a signal electrode driving circuit 2.
A multiplexer 3 comprises an upper switch 31 for switching to the upper reference potentials Vt1 or Vt2 and a lower switch 32 for switching to the lower reference potentials Vb1 or Vb2 at the input sides thereof, the switches 31 and 32 being coupled to the upper reference potential input terminal Vrt and the lower reference potential input terminal Vrb of the 4 - bit A/D converter 1 respectively at the output sides thereof.
A clock .phi.1 produced by a controller 4 is supplied to the multiplexer 3 for controlling the switches 31 and 32 in liaison with each other.
The controller 4 also supplies a signal group .phi.4 including a start signal for timing the start of scanning, a clock for timing the successive shift of a selected pulse, etc. to a scanning electrode driving circuit 5.
Moreover, the A/D converter 1 and the signal electrode driving circuit 2 receive a signal group .phi.3 which is formed mainly on the basis of a horizontal synchronous signal, including a (data sampling clock, a shift clock which forms addresses in the memory 21, a latch clock which transfers data within the memory 21, a signal for timing a pulse width modulation, etc.
The signal electrode driving circuit 2 comprising the memory 21 and a pulse width modulation circuit 22 is coupled to each signal electrode of a liquid crystal panel 6 at each output terminal thereof and a scanning electrode driving circuit 5 is coupled to each scanning electrode of the liquid crystal panel 6 at each out put terminal thereof.
In FIG. 16, the memory 21 transfers all the data to the pulse width modulation circuit 22 after completion of successively reading the 4 - bit data in a cycle of horizontal scanning.
In a display method employing a common line sequential scanning, the A/D converter 1 quantizes a TV signal into 4 - bit data during a first horizontal scanning period and successively stores the same in memory 21. During a second horizontal scanning period, at first the data read by the latch clock of the clock group .phi.3 of the controller 4 is transferred to the pulse width modulation circuit 22.
The pulse width modulation circuit 22 subjects the transferred data to pulse width modulation and supplies the same to the signal electrodes of the liquid crystal panel 6. At that time, the scanning electrode driving circuit 5 supplies selective potentials to corresponding electrodes so as to apply a gradation driving signal to desired pixels together with the waveform produced by the signal electrode driving circuit 2.
Keeping pace therewith, the TV signal during a second horizontal scanning period is quantized into 4 - bit date, which is successively stored in the memory 21. Similarly, the application and sampling of the gradation driving signal are performed at desired pixels during a third horizontal scanning period. A picture is displayed by repeating this process over the entire frame.
A display of 32 gradations according to the dither method in such a system will be described hereinafter. It is supposed that the TV signal inputted to the A/D converter 1 is a raster signal having a uniform luminance and the liquid crystal panel 6 has 240 scanning electrodes for NTSC color system TV display.
Furthermore, the potentials Vt1, Vt2, Vb1 and Vb2 are supposed to have the following relations therebetween: Vt1&lt;Vt2, Vb1&lt;Vb2
The dither method is a method for displaying gradation by way of a plurality of fields, but the vertical resolution of an image is reduced to a half therein.
In the dither method employing two fields, at first in the first field the raster signal is converted to nth gradation using the reference potential couple Vt1 and Vb1 for an A/D conversion, and the resulting potential is applied to pixels.
Next in the second field, the reference potential couple is changed to Vt2 and Vb2 and the A/D converter 1 converts the raster signal to the nth or (n-1)th gradation based on the pulse-height difference. When they are converted to the nth gradation in both of the first and second fields, they are recognized as the nth gradation by sight.
On the other hand, when it is converted into the nth gradation in the first field while the (n-1)th gradation in the second field, they are leveled to be recognized as (n-0.5)th gradation by sight. In this way it is possible to display brightness by 0.5 gradation so as to enable a 32 gradation display using the 4 - bit A/D converter 1.
Supposing that the scanning period of a field is 1/60 second, the scanning period of the dither method comprising the two fields becomes 1/30 second so that there occurs no flicker. The dither method can be also explained on the basis of the responsibility of liquid crystal.
Other methods for gradation display using the binary display liquid crystal panel include a time sharing method and a dot area modulation method. The time sharing method adjusts the average amount of transmitting light by making the time ratio of the transparent state (hereinafter referred to as ON) and the opaque state (hereinafter referred to as OFF) of a pixel correspond to the display gradation. The dot area modulation method divides the pixel into sub-pixels in such a way as to make the area ratio of the ON-state sub-pixels and the OFF-state sub-pixels correspond to the gradation for making use of the spacial leveling effect of sight.
However, various problems are present in the prior art set forth above. The LCD of active matrix driving method employing MIM elements etc. has high contrast which is almost equal to that of CRT. Since in case of CRT the image quality of 64 gradation display is defined as a level wherein the obstruction is recognizable but ignorable, the lowest standard of image quality should be set at the 64 gradation display also in case of the LCD.
In order to realize the 64 gradation display by the pulse width modulation alone, it is enough to subject the signal to a 6 - bit data processing using a 6 - bit A/D converter. However, when the number of bits of the A/D converter is increased by 1, the number of comparators is doubled and the size of the memory used in the driver portion is also doubled, which causes a problem of an enlarged circuit and high cost.
In order to display brightness at 64 gradations according to the dither method using the 4 - bit A/D converter, it is sufficient to display four pictures (four fields in case of TV) in a frame. Four sets of upper and lower reference potentials which are shifted from one another by 1/4 LSB are switched to one another in each picture.
Human eyes recognize brightness in time average when it varies with a frequency more than about 30 Hz, but they recognize the variation of brightness as a flicker when it varies with a frequency less than 30 Hz.
The inventor's experiment proved that when the four upper and lower reference potential couples were switched to each field in displaying TV image, a flicker of about 15 Hz appeared to obstruct the view remarkably. When the multi-gradation display is performed by multiplying the dither method using the small-scale A/D converter in this way, there occurs a problem of generating the flicker difficulty.
Each pixel is divided into sub-pixels in order to perform the multi-gradation display according to the dot area modulation method. As a least dividing method, for example, in case of a 16 gradation display, each pixel is divided into four sub-pixels, the dot area ratio of which is 1:2:4:8, wherein transparent pixels and opaque pixels are selected according to gradation data.
In order to display up to 64 gradations according to this method, each pixel needs to be divided into 6 sub-pixels each of which is driven under independent control. Accordingly, the dot area modulation method has a problem in that the number of pixels has to be increased for multi-gradation display and consequently the number of control lines is also increased.
It is the object of the present invention to solve the problems set forth above and to provide a method of driving an LCD for performing multi-gradation display of high quality using a small-scale A/D converter.